The present invention relates to the field of semiconductor technology. Specifically, embodiments of the invention relate to semiconductor device isolation structures and manufacturing methods.
In analog integrated circuits (IC), in order to obtain good noise immunity, a junction isolation pocket with a buried implant layer can be formed within the substrate. FIG. 1 is a cross-sectional diagram illustrating a conventional semiconductor device in a semiconductor substrate 100. As shown in FIG. 1, a device 103 is disposed in an isolation pocket having a doped polysilicon 102 in a deep trench structure at the side of a buried layer 101.
However, the inventors have observed that subsequent thermal processing can cause diffusion in the buried layer and out-diffusion from the doped polysilicon in the isolation pocket. These diffusion regions can impose a limit on device spacing and lead to larger die size of the integrated circuit.
Therefore, an improved device isolation method and structure is highly desirable.